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SEnior Digital Design Engineer

POSITION DESCRIPTION

We are seeking a highly skilled and analytical Senior FPGA/Digital Design Engineer to join our team. In this role, you will bridge the gap between high-level modeling and hardware realization, specifically focused on translating complex MATLAB algorithms into optimized Verilog code. You will play a critical role in defining hardware interfaces between FPGAs and digital drive circuitry, as well as designing and optimizing hybrid drive-sense architectures. The ideal candidate will possess deep expertise in timing architecture design, hardware optimization, and maintaining an intimate knowledge of the current state of the technology to drive critical component selection and engineering decisions.

Employment Type: Full-Time Salaried

Primary Location: USA-CA-Pleasanton

RESPONSIBILITIES:

  • Algorithm-to-Hardware Translation: Translate, refactor, and implement complex MATLAB/Simulink algorithms into efficient Verilog/SystemVerilog code for FPGA deployment.

  • Interface Definition & Design: Define, document, and implement robust digital communication interfaces and protocol layers between high-speed FPGAs and peripheral digital/analog drive circuitry.

  • Hybrid Drive-Sense Systems: Design and integrate digital logic for complex hybrid drive-sense architectures, ensuring precise synchronization, signal integrity, and low-latency feedback loops.

  • Timing Architecture & Closure: Architect and implement comprehensive clocking and timing structures, managing multi-clock domain crossings (CDC) and achieving strict timing closure on high-utilization designs.

  • Hardware Optimization: Analyze and optimize FPGA resources (LUTs, DSPs, BRAMs) and code performance to improve key metrics such as throughput, latency, power consumption, and clock frequency.

  • Component Selection & Architecture: Leverage deep familiarity with the current state of technology (FPGA families, ADCs/DACs, high-speed drivers) to conduct trade studies, select appropriate hardware components, and make critical engineering decisions.

  • Verification & Validation: Develop testbenches and simulation frameworks to validate Verilog RTL against MATLAB golden models, and perform hands-on hardware bring-up and debugging using lab equipment (oscilloscopes, logic analyzers).

BASIC QUALIFICATIONS:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related technical field.

  • 5+ years of experience in FPGA/ASIC design, verification, and implementation using Verilog or SystemVerilog.

  • Proven experience manually translating and optimizing algorithms from MATLAB/Simulink into hardware-efficient RTL.

  • Strong background in timing architecture design, including constraint generation (SDC/XDC), static timing analysis (STA), and clock domain crossing mitigation.

  • Hands-on experience interface-mapping and integrating FPGAs with external digital/analog circuitry (e.g., SPI, I2C, PCIe, or custom high-speed parallel buses).

PREFERRED QUALIFICATIONS:

An ideal candidate would have familiarity with:

  • Experience designing hybrid mixed-signal or drive-sense circuitry loops (e.g., precision beam steering, high-density optical networking controls, or autonomous robotics sensing).

  • Deep understanding of modern FPGA architectures (e.g., AMD/Xilinx UltraScale+, Intel Stratix/Agilex) and advanced toolchains (Vivado, Quartus Prime).

  • Familiarity with hardware/software co-design, embedded processors (e.g., ARM Cortex, MicroBlaze), or SoC architectures.

  • Demonstrated track record of leading component-selection trade studies for aerospace, defense, or high-reliability commercial hardware environments.

  • Experience with automated MATLAB HDL Coder workflows, complemented by the ability to write clean, hand-optimized RTL when automated tools fall short.

Don't meet every single requirement? Studies have shown that women and people of color are less likely to apply to jobs unless they meet every single qualification. At BST we are dedicated to building a diverse, inclusive and authentic workplace, so if you're excited about this role but your past experience doesn't align perfectly with every qualification in the job description, we encourage you to apply anyways. You may be just the right candidate for this or other roles. 

COMPANY OVERVIEW

At Bright we are building precision optical systems to guide data for a new era of communication.  Our technology introduces an unprecedented level of precision, agility, and versatility to directing light. We are experts in precision engineering, optical design and product development who are delivering technological breakthroughs to revolutionize photonics.  The LDA has the potential to revolutionize optical system markets such as laser communication terminals for terrestrial and satellite mesh networks, optical switching for data centers, LIDAR for autonomous car and drones, 3D printing of metals, and many others. 

Founded in 2020, Bright Silicon Technologies’ goal is to build an enduring technology manufacturing company, with first product to market in 2026.  In this position, you will play a critical role in the creation, launch, and scaling of a new advanced technology product.  We offer competitive market salaries as well as equity incentives so that every team member owns a piece of our success.  We’re an engineer-led company, and we value efficiently and effectively completing our work while sustaining a long-term work/life balance. 

The company offers a total rewards package that is competitive and comprehensive including, but not limited to the following:

  • Equity Incentive Plan – Restricted Stock Awards

  • Comprehensive medical, dental and vision along with other voluntary benefits

  • 3% employer contribution to employee 401(K)

  • Development and career growth opportunities

  • Generous paid time off and paid company holidays

EEO STATEMENT

Bright Silicon Technologies is an equal opportunity employer to all, regardless of age, ancestry, association with a member of a protected class, bereavement leave, color, disability (physical, intellectual/developmental, or mental health/psychiatric), exercising the right to family care and medical leave related to serious health condition of employee or family member, child bonding, or military exigencies, engaging in protected activity, gender identity or expression, genetic information or characteristic, marital status, medical condition (cancer or genetic characteristic), military and veteran status, national origin (includes language restrictions), pregnancy, childbirth, breastfeeding, or related medical conditions, Pregnancy Disability Leave (PDL), race (includes hairstyle and hair texture), religious creed (includes dress and grooming practices), reproductive health decision making, sex/gender, and sexual orientation.

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